rcc_reg.h File Reference

#include "common/hal_types.h"
#include <stdint.h>

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Classes
struct	RCC_Typedef
	RCC register map structure. More...

Macros
#define	RCC_BASE_ADDR   0x40023800
	RCC base address.
#define	RCC   ((RCC_Typedef *)RCC_BASE_ADDR)
	Pointer to RCC peripheral registers.
#define	RCC_ON   0x1
	Enable flag.
#define	RCC_OFF   0x0
	Disable flag.
#define	RCC_CR_HSE_ON_BIT   16
#define	RCC_CR_HSE_READY_BIT   17
#define	RCC_CR_HSI_ON_BIT   0
#define	RCC_CR_HSI_READY_BIT   1
#define	RCC_CR_PLL_ON_BIT   24
#define	RCC_CR_PLL_READY_BIT   25
#define	RCC_CR_HSEON   (1 << RCC_CR_HSE_ON_BIT)
#define	RCC_CR_HSERDY   (1 << RCC_CR_HSE_READY_BIT)
#define	RCC_CR_HSION   (1 << RCC_CR_HSI_ON_BIT)
#define	RCC_CR_HSIRDY   (1 << RCC_CR_HSI_READY_BIT)
#define	RCC_CR_PLLON   (1 << RCC_CR_PLL_ON_BIT)
#define	RCC_CR_PLLRDY   (1 << RCC_CR_PLL_READY_BIT)
#define	RCC_PLLCFGR_SRC_BIT   22
#define	RCC_PLLCFGR_PLLM_BIT   0
#define	RCC_PLLCFGR_PLLN_BIT   6
#define	RCC_PLLCFGR_PLLP_BIT   16
#define	RCC_PLLCFGR_PLLQ_BIT   24
#define	RCC_PLLCFGR_SRC   (1 << RCC_PLLCFGR_SRC_BIT)
#define	RCC_PLLCFGR_PLLM(m)
#define	RCC_PLLCFGR_PLLN(n)
#define	RCC_PLLCFGR_PLLP(p)
#define	RCC_PLLCFGR_PLLQ(q)
#define	RCC_CFGR_HPRE_BIT   4
#define	RCC_CFGR_PPRE1_BIT   10
#define	RCC_CFGR_PPRE2_BIT   13
#define	RCC_CFGR_SW_BIT   0
#define	RCC_CFGR_SWS_BIT   2
#define	RCC_CFGR_HPRE_MASK   (0xF << RCC_CFGR_HPRE_BIT)
#define	RCC_CFGR_PPRE1_MASK   (0x7 << RCC_CFGR_PPRE1_BIT)
#define	RCC_CFGR_PPRE2_MASK   (0x7 << RCC_CFGR_PPRE2_BIT)
#define	RCC_CFGR_HPRE_DIV(n)
#define	RCC_CFGR_PPRE1_DIV(n)
#define	RCC_CFGR_PPRE2_DIV(n)
#define	RCC_CFGR_HPRE_DIV1   0x0
#define	RCC_CFGR_PPRE1_DIV4   0x5
#define	RCC_CFGR_PPRE2_DIV2   0x4

Enumerations
enum	rcc_cfgr_hpre_div_t {   RCC_CFGR_HPRE_DIV1 = 0x0 , RCC_CFGR_HPRE_DIV2 = 0x8 , RCC_CFGR_HPRE_DIV4 = 0x9 , RCC_CFGR_HPRE_DIV8 = 0xA ,   RCC_CFGR_HPRE_DIV16 = 0xB , RCC_CFGR_HPRE_DIV64 = 0xC , RCC_CFGR_HPRE_DIV128 = 0xD , RCC_CFGR_HPRE_DIV256 = 0xE ,   RCC_CFGR_HPRE_DIV512 = 0xF }
	AHB prescaler division factors. More...
enum	rcc_cfgr_ppre_div_t {   RCC_CFGR_PPRE_DIV1 = 0x0 , RCC_CFGR_PPRE_DIV2 = 0x4 , RCC_CFGR_PPRE_DIV4 = 0x5 , RCC_CFGR_PPRE_DIV8 = 0x6 ,   RCC_CFGR_PPRE_DIV16 = 0x7 }
	APB prescaler division factors. More...

Macro Definition Documentation

RCC

#define RCC   ((RCC_Typedef *)RCC_BASE_ADDR)

Pointer to RCC peripheral registers.

RCC_BASE_ADDR

#define RCC_BASE_ADDR   0x40023800

RCC base address.

RCC_CFGR_HPRE_BIT

#define RCC_CFGR_HPRE_BIT   4

AHB prescaler bits

RCC_CFGR_HPRE_DIV

#define RCC_CFGR_HPRE_DIV

(

n

)

Value:

(n << RCC_CFGR_HPRE_BIT)

Set AHB prescaler

RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV1   0x0

AHB clock not divided

RCC_CFGR_HPRE_MASK

#define RCC_CFGR_HPRE_MASK   (0xF << RCC_CFGR_HPRE_BIT)

Mask for AHB prescaler

RCC_CFGR_PPRE1_BIT

#define RCC_CFGR_PPRE1_BIT   10

APB1 prescaler bits

RCC_CFGR_PPRE1_DIV

#define RCC_CFGR_PPRE1_DIV

(

n

)

Value:

(n << RCC_CFGR_PPRE1_BIT)

Set APB1 prescaler

RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV4   0x5

APB1 clock = HCLK / 4

RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK   (0x7 << RCC_CFGR_PPRE1_BIT)

Mask for APB1 prescaler

RCC_CFGR_PPRE2_BIT

#define RCC_CFGR_PPRE2_BIT   13

APB2 prescaler bits

RCC_CFGR_PPRE2_DIV

#define RCC_CFGR_PPRE2_DIV

(

n

)

Value:

(n << RCC_CFGR_PPRE2_BIT)

Set APB2 prescaler

RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV2   0x4

APB2 clock = HCLK / 2

RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK   (0x7 << RCC_CFGR_PPRE2_BIT)

Mask for APB2 prescaler

RCC_CFGR_SW_BIT

#define RCC_CFGR_SW_BIT   0

System clock switch bits

RCC_CFGR_SWS_BIT

#define RCC_CFGR_SWS_BIT   2

System clock switch status bits

RCC_CR_HSE_ON_BIT

#define RCC_CR_HSE_ON_BIT   16

HSE clock enable bit

RCC_CR_HSE_READY_BIT

#define RCC_CR_HSE_READY_BIT   17

HSE clock ready flag

RCC_CR_HSEON

#define RCC_CR_HSEON   (1 << RCC_CR_HSE_ON_BIT)

Enable external HSE clock

RCC_CR_HSERDY

#define RCC_CR_HSERDY   (1 << RCC_CR_HSE_READY_BIT)

External HSE clock ready flag

RCC_CR_HSI_ON_BIT

#define RCC_CR_HSI_ON_BIT   0

HSI clock enable bit

RCC_CR_HSI_READY_BIT

#define RCC_CR_HSI_READY_BIT   1

HSI clock ready flag

RCC_CR_HSION

#define RCC_CR_HSION   (1 << RCC_CR_HSI_ON_BIT)

Enable internal HSI clock

RCC_CR_HSIRDY

#define RCC_CR_HSIRDY   (1 << RCC_CR_HSI_READY_BIT)

Internal HSI clock ready flag

RCC_CR_PLL_ON_BIT

#define RCC_CR_PLL_ON_BIT   24

PLL enable bit

RCC_CR_PLL_READY_BIT

#define RCC_CR_PLL_READY_BIT   25

PLL ready flag

RCC_CR_PLLON

#define RCC_CR_PLLON   (1 << RCC_CR_PLL_ON_BIT)

Enable PLL

RCC_CR_PLLRDY

#define RCC_CR_PLLRDY   (1 << RCC_CR_PLL_READY_BIT)

PLL ready flag

RCC_OFF

#define RCC_OFF   0x0

Disable flag.

RCC_ON

#define RCC_ON   0x1

Enable flag.

RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM

(

m

)

Value:

(((m) & 0x3F) << RCC_PLLCFGR_PLLM_BIT)

Set PLLM

RCC_PLLCFGR_PLLM_BIT

#define RCC_PLLCFGR_PLLM_BIT   0

PLLM bits

RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN

(

n

)

Value:

(((n) & 0x1FF) << RCC_PLLCFGR_PLLN_BIT)

Set PLLN

RCC_PLLCFGR_PLLN_BIT

#define RCC_PLLCFGR_PLLN_BIT   6

PLLN bits

RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP

(

p

)

Value:

((((p) >> 1) - 1) << RCC_PLLCFGR_PLLP_BIT)

Set PLLP

RCC_PLLCFGR_PLLP_BIT

#define RCC_PLLCFGR_PLLP_BIT   16

PLLP bits

RCC_PLLCFGR_PLLQ

#define RCC_PLLCFGR_PLLQ

(

q

)

Value:

(((q) & 0x0F) << RCC_PLLCFGR_PLLQ_BIT)

Set PLLQ

RCC_PLLCFGR_PLLQ_BIT

#define RCC_PLLCFGR_PLLQ_BIT   24

PLLQ bits

RCC_PLLCFGR_SRC

#define RCC_PLLCFGR_SRC   (1 << RCC_PLLCFGR_SRC_BIT)

0: HSI, 1: HSE

RCC_PLLCFGR_SRC_BIT

#define RCC_PLLCFGR_SRC_BIT   22

PLL source selection bit

Enumeration Type Documentation

rcc_cfgr_hpre_div_t

enum rcc_cfgr_hpre_div_t

AHB prescaler division factors.

Enumerator
RCC_CFGR_HPRE_DIV1	SYSCLK not divided
RCC_CFGR_HPRE_DIV2	SYSCLK divided by 2
RCC_CFGR_HPRE_DIV4	SYSCLK divided by 4
RCC_CFGR_HPRE_DIV8	SYSCLK divided by 8
RCC_CFGR_HPRE_DIV16	SYSCLK divided by 16
RCC_CFGR_HPRE_DIV64	SYSCLK divided by 64
RCC_CFGR_HPRE_DIV128	SYSCLK divided by 128
RCC_CFGR_HPRE_DIV256	SYSCLK divided by 256
RCC_CFGR_HPRE_DIV512	SYSCLK divided by 512

rcc_cfgr_ppre_div_t

enum rcc_cfgr_ppre_div_t

APB prescaler division factors.

Enumerator
RCC_CFGR_PPRE_DIV1	HCLK not divided
RCC_CFGR_PPRE_DIV2	HCLK divided by 2
RCC_CFGR_PPRE_DIV4	HCLK divided by 4
RCC_CFGR_PPRE_DIV8	HCLK divided by 8
RCC_CFGR_PPRE_DIV16	HCLK divided by 16