rcc_reg.h

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#ifndef CORTEX_M4_RCC_REG_H
#define CORTEX_M4_RCC_REG_H
 
#include "common/hal_types.h"
#include <stdint.h>

typedef struct {
  __IO uint32_t CR;          
  __IO uint32_t PLLCFGR;     
  __IO uint32_t CFGR;        
  __IO uint32_t CIR;         
  __IO uint32_t AHB1RSTR;    
  __IO uint32_t AHB2RSTR;    
  __IO uint32_t RESERVED_18; 
  __IO uint32_t RESERVED_1C; 
  __IO uint32_t APB1RSTR;    
  __IO uint32_t APB2RSTR;    
  __IO uint32_t RESERVED_28; 
  __IO uint32_t RESERVED_2C; 
  __IO uint32_t AHB1ENR;     
  __IO uint32_t AHB2ENR;     
  __IO uint32_t RESERVED_38; 
  __IO uint32_t RESERVED_3C; 
  __IO uint32_t APB1ENR;     
  __IO uint32_t APB2ENR;     
  __IO uint32_t RESERVED_48; 
  __IO uint32_t RESERVED_4C; 
  __IO uint32_t AHB1LPENR;   
  __IO uint32_t AHB2LPENR;   
  __IO uint32_t RESERVED_58; 
  __IO uint32_t RESERVED_5C; 
  __IO uint32_t APB1LPENR;   
  __IO uint32_t APB2LPENR;   
  __IO uint32_t RESERVED_68; 
  __IO uint32_t RESERVED_6C; 
  __IO uint32_t BDCR;        
  __IO uint32_t CSR;         
  __IO uint32_t RESERVED_78; 
  __IO uint32_t RESERVED_7C; 
  __IO uint32_t SSCGR;       
  __IO uint32_t PLLI2SCFGR;  
  __IO uint32_t RESERVED_88; 
  __IO uint32_t DCKCFGR;     
} RCC_Typedef;

#define RCC_BASE_ADDR 0x40023800

#define RCC ((RCC_Typedef *)RCC_BASE_ADDR)

#define RCC_ON 0x1
#define RCC_OFF 0x0
 
/* RCC_CR bit positions */
#define RCC_CR_HSE_ON_BIT 16    
#define RCC_CR_HSE_READY_BIT 17 
#define RCC_CR_HSI_ON_BIT 0     
#define RCC_CR_HSI_READY_BIT 1  
#define RCC_CR_PLL_ON_BIT 24    
#define RCC_CR_PLL_READY_BIT 25 
 
/* RCC_CR masks */
#define RCC_CR_HSEON (1 << RCC_CR_HSE_ON_BIT)   
#define RCC_CR_HSERDY (1 << RCC_CR_HSE_READY_BIT) 
#define RCC_CR_HSION (1 << RCC_CR_HSI_ON_BIT)   
#define RCC_CR_HSIRDY (1 << RCC_CR_HSI_READY_BIT) 
#define RCC_CR_PLLON (1 << RCC_CR_PLL_ON_BIT)   
#define RCC_CR_PLLRDY (1 << RCC_CR_PLL_READY_BIT) 
 
/* RCC_PLLCFGR bit positions */
#define RCC_PLLCFGR_SRC_BIT 22  
#define RCC_PLLCFGR_PLLM_BIT 0  
#define RCC_PLLCFGR_PLLN_BIT 6  
#define RCC_PLLCFGR_PLLP_BIT 16 
#define RCC_PLLCFGR_PLLQ_BIT 24 
 
/* RCC_PLLCFGR masks */
#define RCC_PLLCFGR_SRC (1 << RCC_PLLCFGR_SRC_BIT) 
#define RCC_PLLCFGR_PLLM(m) (((m) & 0x3F) << RCC_PLLCFGR_PLLM_BIT) 
#define RCC_PLLCFGR_PLLN(n) (((n) & 0x1FF) << RCC_PLLCFGR_PLLN_BIT) 
#define RCC_PLLCFGR_PLLP(p) ((((p) >> 1) - 1) << RCC_PLLCFGR_PLLP_BIT) 
#define RCC_PLLCFGR_PLLQ(q) (((q) & 0x0F) << RCC_PLLCFGR_PLLQ_BIT) 
 
/* RCC_CFGR bit positions */
#define RCC_CFGR_HPRE_BIT 4   
#define RCC_CFGR_PPRE1_BIT 10 
#define RCC_CFGR_PPRE2_BIT 13 
#define RCC_CFGR_SW_BIT 0     
#define RCC_CFGR_SWS_BIT 2    
 
/* RCC_CFGR masks */
#define RCC_CFGR_HPRE_MASK (0xF << RCC_CFGR_HPRE_BIT) 
#define RCC_CFGR_PPRE1_MASK (0x7 << RCC_CFGR_PPRE1_BIT) 
#define RCC_CFGR_PPRE2_MASK (0x7 << RCC_CFGR_PPRE2_BIT) 

typedef enum {
  RCC_CFGR_HPRE_DIV1 = 0x0,   
  RCC_CFGR_HPRE_DIV2 = 0x8,   
  RCC_CFGR_HPRE_DIV4 = 0x9,   
  RCC_CFGR_HPRE_DIV8 = 0xA,   
  RCC_CFGR_HPRE_DIV16 = 0xB,  
  RCC_CFGR_HPRE_DIV64 = 0xC,  
  RCC_CFGR_HPRE_DIV128 = 0xD, 
  RCC_CFGR_HPRE_DIV256 = 0xE, 
  RCC_CFGR_HPRE_DIV512 = 0xF  
} rcc_cfgr_hpre_div_t;

typedef enum {
  RCC_CFGR_PPRE_DIV1 = 0x0,  
  RCC_CFGR_PPRE_DIV2 = 0x4,  
  RCC_CFGR_PPRE_DIV4 = 0x5,  
  RCC_CFGR_PPRE_DIV8 = 0x6,  
  RCC_CFGR_PPRE_DIV16 = 0x7  
} rcc_cfgr_ppre_div_t;
 
#define RCC_CFGR_HPRE_DIV(n) (n << RCC_CFGR_HPRE_BIT)   
#define RCC_CFGR_PPRE1_DIV(n) (n << RCC_CFGR_PPRE1_BIT) 
#define RCC_CFGR_PPRE2_DIV(n) (n << RCC_CFGR_PPRE2_BIT) 
 
/* Common predefined prescaler values */
#define RCC_CFGR_HPRE_DIV1 0x0  
#define RCC_CFGR_PPRE1_DIV4 0x5 
#define RCC_CFGR_PPRE2_DIV2 0x4 
 
#endif // !CORTEX_M4_RCC_REG_H