
Macros | |
| #define | CORTEX_M4 |
| #define | PERIPH_BASE 0x40000000UL |
| #define | AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define | APB1PERIPH_BASE (PERIPH_BASE + 0x00000000UL) |
| #define | GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) |
| #define | RCC_BASE (AHB1PERIPH_BASE + 0x3800) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define | RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x30)) |
| #define | RCC_APB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x40)) |
| #define | GPIOA_MODER (*(volatile uint32_t *)(GPIOA_BASE + 0x00)) |
| #define | GPIOA_AFRL (*(volatile uint32_t *)(GPIOA_BASE + 0x20)) |
| #define | USART2_SR (*(volatile uint32_t *)(USART2_BASE + 0x00)) |
| #define | USART2_DR (*(volatile uint32_t *)(USART2_BASE + 0x04)) |
| #define | USART2_BRR (*(volatile uint32_t *)(USART2_BASE + 0x08)) |
| #define | USART2_CR1 (*(volatile uint32_t *)(USART2_BASE + 0x0C)) |
| #define | RCC_AHB1ENR_GPIOAEN (1 << 0) |
| #define | RCC_APB1ENR_USART2EN (1 << 17) |
| #define | USART_CR1_UE (1 << 13) |
| #define | USART_CR1_TE (1 << 3) |
| #define | USART_SR_TXE (1 << 7) |
Functions | |
| void | delay (volatile uint32_t count) |
| void | uart2_init (void) |
| void | uart2_write_char (char c) |
| void | uart2_write_int (int num) |
| void | uart2_write_string (const char *s) |
| int | main (void) |
Variables | |
| hal_clock_config_t | clk_cfg |
| hal_pll_config_t | pll_cfg |
| #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000UL) |
| #define CORTEX_M4 |
| #define GPIOA_AFRL (*(volatile uint32_t *)(GPIOA_BASE + 0x20)) |
| #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) |
| #define GPIOA_MODER (*(volatile uint32_t *)(GPIOA_BASE + 0x00)) |
| #define PERIPH_BASE 0x40000000UL |
| #define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x30)) |
| #define RCC_AHB1ENR_GPIOAEN (1 << 0) |
| #define RCC_APB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x40)) |
| #define RCC_APB1ENR_USART2EN (1 << 17) |
| #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define USART2_BRR (*(volatile uint32_t *)(USART2_BASE + 0x08)) |
| #define USART2_CR1 (*(volatile uint32_t *)(USART2_BASE + 0x0C)) |
| #define USART2_DR (*(volatile uint32_t *)(USART2_BASE + 0x04)) |
| #define USART2_SR (*(volatile uint32_t *)(USART2_BASE + 0x00)) |
| #define USART_CR1_TE (1 << 3) |
| #define USART_CR1_UE (1 << 13) |
| #define USART_SR_TXE (1 << 7) |
| void delay | ( | volatile uint32_t | count | ) |
| int main | ( | void | ) |
| void uart2_init | ( | void | ) |
| void uart2_write_int | ( | int | num | ) |
| hal_clock_config_t clk_cfg |
| hal_pll_config_t pll_cfg |