TIMx_Reg_Typedef Struct Reference

#include <timer_reg.h>

Public Attributes
__IO uint32_t	CR1
__IO uint32_t	CR2
__IO uint32_t	SMCR
__IO uint32_t	DIER
__IO uint32_t	SR
__IO uint32_t	EGR
__IO uint32_t	CCMR1
__IO uint32_t	CCMR2
__IO uint32_t	CCER
__IO uint32_t	CNT
__IO uint32_t	PSC
__IO uint32_t	ARR
__IO uint32_t	RCR
__IO uint32_t	CCR1
__IO uint32_t	CCR2
__IO uint32_t	CCR3
__IO uint32_t	CCR4
__IO uint32_t	BDTR
__IO uint32_t	DCR
__IO uint32_t	DMAR
__IO uint32_t	OR

Member Data Documentation

ARR

__IO uint32_t TIMx_Reg_Typedef::ARR

0x2C: Auto-reload register (All timers; width depends on timer)

BDTR

__IO uint32_t TIMx_Reg_Typedef::BDTR

0x44: Break and dead-time register (Only TIM1, TIM8 — reserved otherwise)

CCER

__IO uint32_t TIMx_Reg_Typedef::CCER

0x20: Capture/Compare enable register (All except TIM6, TIM7 — reserved)

CCMR1

__IO uint32_t TIMx_Reg_Typedef::CCMR1

0x18: Capture/Compare mode register 1 (All except TIM6, TIM7 — reserved)

CCMR2

__IO uint32_t TIMx_Reg_Typedef::CCMR2

0x1C: Capture/Compare mode register 2 (All except TIM6, TIM7 — reserved)

CCR1

__IO uint32_t TIMx_Reg_Typedef::CCR1

0x34: Capture/Compare register 1 (All except TIM6, TIM7 — reserved)

CCR2

__IO uint32_t TIMx_Reg_Typedef::CCR2

0x38: Capture/Compare register 2 (All except TIM6, TIM7 — reserved)

CCR3

__IO uint32_t TIMx_Reg_Typedef::CCR3

0x3C: Capture/Compare register 3 (Only TIM1–TIM5, TIM8; reserved otherwise)

CCR4

__IO uint32_t TIMx_Reg_Typedef::CCR4

0x40: Capture/Compare register 4 (Only TIM1–TIM5, TIM8; reserved otherwise)

CNT

__IO uint32_t TIMx_Reg_Typedef::CNT

0x24: Counter (All timers; width depends on timer: TIM2/TIM5=32-bit, others=16-bit)

CR1

__IO uint32_t TIMx_Reg_Typedef::CR1

0x00: Control register 1 (All timers)

CR2

__IO uint32_t TIMx_Reg_Typedef::CR2

0x04: Control register 2 (All timers; basic timers use only some bits)

DCR

__IO uint32_t TIMx_Reg_Typedef::DCR

0x48: DMA control register (All timers except TIM6, TIM7)

DIER

__IO uint32_t TIMx_Reg_Typedef::DIER

0x0C: DMA/Interrupt enable register (All timers)

DMAR

__IO uint32_t TIMx_Reg_Typedef::DMAR

0x4C: DMA address for full transfer (All timers except TIM6, TIM7)

EGR

__IO uint32_t TIMx_Reg_Typedef::EGR

0x14: Event generation register (All timers)

OR

__IO uint32_t TIMx_Reg_Typedef::OR

0x50: Option register (Only TIM2, TIM5, TIM9–TIM11; reserved otherwise)

PSC

__IO uint32_t TIMx_Reg_Typedef::PSC

0x28: Prescaler (All timers)

RCR

__IO uint32_t TIMx_Reg_Typedef::RCR

0x30: Repetition counter register (Only TIM1, TIM8, TIM9–TIM11; reserved otherwise)

SMCR

__IO uint32_t TIMx_Reg_Typedef::SMCR

0x08: Slave mode control register (All except TIM6, TIM7 — reserved)

SR

__IO uint32_t TIMx_Reg_Typedef::SR

0x10: Status register (All timers)

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The documentation for this struct was generated from the following file:

• include/core/cortex-m4/timer_reg.h