21#ifndef CORTEX_M4_GPIO_REG_H
22#define CORTEX_M4_GPIO_REG_H
57#define GPIOA_BASE_ADDR 0x40020000
58#define GPIOB_BASE_ADDR 0x40020400
59#define GPIOC_BASE_ADDR 0x40020800
60#define GPIOD_BASE_ADDR 0x40020C00
61#define GPIOE_BASE_ADDR 0x40021000
62#define GPIOH_BASE_ADDR 0x40021C00
65#define GPIO_GET_PORT_NUMBER(n) (n / 16 == 5 ? 7 : n / 16)
68#define GPIO_GET_PORT(n) \
69 ((GPIOx_Typedef *)(GPIOA_BASE_ADDR + ((GPIO_GET_PORT_NUMBER(n)) * 0x400)))
72#define GPIO_GET_PIN(n) (n % 16)
#define __IO
Definition hal_types.h:20
GPIO port register structure.
Definition gpio_reg.h:43
volatile uint32_t IDR
Definition gpio_reg.h:48
volatile uint32_t BSRR
Definition gpio_reg.h:50
volatile uint32_t ODR
Definition gpio_reg.h:49
volatile uint32_t AFRL
Definition gpio_reg.h:52
volatile uint32_t OSPEEDR
Definition gpio_reg.h:46
volatile uint32_t MODER
Definition gpio_reg.h:44
volatile uint32_t LCKR
Definition gpio_reg.h:51
volatile uint32_t AFRH
Definition gpio_reg.h:53
volatile uint32_t PUPDR
Definition gpio_reg.h:47
volatile uint32_t OTYPER
Definition gpio_reg.h:45
Centralized type definitions include for NavHAL.